Voltage tunable active inductorless filter

ABSTRACT

A monolithic active frequency selection circuit includes an input presenting a frequency-dependent impedance and a first gain block configured to provide less than unity voltage gain, a high input impedance and a low output impedance. An output of the first amplifier is coupled to the frequency selection circuit input. The frequency selection circuit includes a first phase shifter that, in one aspect, is formed by a first capacitor coupled between the first port and a reference voltage. The frequency selection circuit also includes a second amplifier configured to provide greater than unity voltage gain. The second amplifier has an input coupled to the output of the first amplifier and an output coupled to the input of the first amplifier. The frequency selection circuit further includes a second phase shifter, which may be formed from a capacitor coupled between the output of the second amplifier and a reference voltage. The first and second amplifiers and the first and second phase shifters are coupled in a loop such that the frequency dependence of an impedance presented at the output of the first amplifier emulates the impedance of a parallel RLC tank circuit, providing a Q on the order of ten at a center frequency ω o  of several hundred megahertz. The output of the second amplifier may be used to provide a high Q, tuned transimpedance amplification function relative to the input.

TECHNICAL FIELD

[0001] The present invention relates in general to monolithic radiofrequency circuits and in particular to improved monolithic voltagetunable filters.

BACKGROUND OF THE INVENTION

[0002] Wireless communications products have become high volume consumerelectronics accessories and are in increasing demand for a broad varietyof applications. Features that are increasingly emphasized includereduced power consumption, small form factor, light weight andportability. Many of these products operate in a frequency rangeextending from about one hundred megahertz to about two gigahertz. As aresult, there is a demand to integrate RF receivers and transmittersinto high-yield silicon integrated circuit processes to allow acombination of analog, digital and RF functions on a single integratedcircuit. “Applications for GaAs and Silicon Integrated Circuits in NextGeneration Wireless Communication Systems,” by L. M. Burns, IEEE JSSC,Vol. 30, No. 10, Oct. 1995, pp. 1088-1095, discusses examples ofmonolithic radio receiver and transmitter functions.

[0003] Most radio receivers and transmitters require frequency selectioncomponents that rely on some form of oscillation to provide frequencyselectivity. Devices such as crystals and SAWs that employ mechanicalvibration to realize frequency selection also require hermetic packageshaving interior cavities in order to provide reliable and robustelectrical characteristics, particularly in view of environmentalhazards. Often, the package is more expensive than the component withinit. Additionally, multiple packages are required, because the materialsuseful for these types of frequency selection components do not supportactive electronic devices, and vice versa. Further, devices that rely onmechanical oscillation also use materials having different packagingrequirements than do active electronic devices.

[0004] Electronic circuits that do not rely on mechanical vibrations forfrequency selection characteristics often rely instead on electricalresonances to provide frequency selectivity. Practical electricalresonators in this frequency range require a combination of capacitanceand inductance. Of these, inductance is particularly difficult torealize in compact form together with reasonably high quality factor, or“Q.” Q is often defined as the amount of energy stored divided by theamount of energy dissipated per cycle, but can also be defined as acenter frequency divided by a three dB bandwidth of a frequencyresponse. The latter definition is used herein in instances where theformer is inapplicable.

[0005] Known approaches for realizing monolithic inductance includespiral inductors, transmission lines and bond wires. For example, “A 1.8GHz Low-Phase-Noise Spiral-LC CMOS VCO,” by J. Cranickx and M. Steyaert,1996 Symp. on VLSI Cir. Dig. Tech. Papers, pp. 30-31 describes a spiralinductor approach that achieves a Q of 5.7 near two gigahertz.“Integrated Passive Components in MCM-Si Technology and theirApplications in RF-Systems,” by J. Hartung, 1998 Int. Conf. on MultichipModules and High Density Packaging, IEEE Cat. No. 0-7803-4850-8/98, pp.256-261, reports Qs and their frequency dependence for spiral inductorsvs. substrate resistance, with highest Qs and self-resonant frequenciesfor spiral inductors fabricated on higher-resistivity substrates. Arecent overview of spiral inductive components, entitled “Analysis,Design, and Optimization of Spiral Inductors and Transformers for Si RFIC's,” by A. Niknejad and R. Meyer, IEEE JSSC, Vol. 33, No. 10, Oct.1998, pp. 1470-1481, gives examples of Qs having peak values around fiveand inductances of up to about ten nanoHenrys for spiral inductorsfabricated on silicon.

[0006] Transmission line approaches to realizing monolithic inductancetend to be bulky and relatively lossy in this frequency range. Bondwires can provide Qs ranging from 11 to 15, as described in “A 1V, 1.8GHz, Balanced Voltage-Controlled Oscillator with an IntegratedResonator,” by D. A. Hitko et al., Proc. Symp. Low Power Electr. andDes., pp. 46-51 (1997). Bond wire inductors tend to be relatively largecompared to other integrated circuit components, but do permit thesurface area beneath them to be used to fabricate other integratedcircuit elements prior to bond wire installation. Bond wire inductorsalso require bond pads, which are relatively large and which alsopreclude use of their area for other purposes. None of these approachesprovide the combination of small form factor, high Q and packageabilityneeded for many applications.

[0007] Another approach to providing a frequency selection function inmonolithic form relies on impedance transformations that are possiblewith active circuits, i.e., circuits including transistors. U.S. Pat.No. 5,175,513, entitled “Oscillator Circuit Employing Inductive CircuitFormed of Field Effect Transistors” and issued to S. Hara, describes anexample using MESFETs. U.S. Pat. No. 5,726,613, entitled, “ActiveInductor,” issued to H. Hayashi et al. and “A Novel Broad-Band MMIC VCOUsing an Active Inductor,” H. Hayashi and M. Maraguchi, IEICE Trans.Fundamentals, Vol. E81-A, No. 2, Feb. 1998, pp. 224-229, describesimilar approaches. While these approaches do provide compact circuits,they use GaAs MESFETs, which are not as manufacturable as CMOS FETs andwhich are not cost-competitive with silicon integrated circuits.Additionally, it is much more expensive to provide complex ancillaryfunctions on GaAs substrates, such as may be realized using digitalcircuitry, than is the case with silicon substrates.

[0008] Therefore, there is a need for monolithic circuitry that providesfrequency selection functions and that is compatible with cost-effectiveapproaches to providing other circuit functions.

SUMMARY OF THE INVENTION

[0009] In one aspect, the present invention includes an active frequencyselection circuit. The frequency selection circuit includes a first portpresenting a frequency-dependent impedance and a first amplifierconfigured to provide nearly unity gain, a high input impedance and alow output impedance. The first amplifier has a first input and a firstoutput. The first output is coupled to the first port. The frequencyselection circuit includes a first phase shifter that, in one aspect, isformed by a first capacitor coupled between the first port and areference voltage. The frequency selection circuit also includes asecond amplifier configured to provide greater than unity voltage gain,a high input impedance and a low output impedance. The second amplifierhas a second input coupled to the first output and a second outputcoupled to the first input through a second phase shifter. In oneaspect, the second phase shifter is formed from a second capacitorcoupled between the second output and a reference voltage. The first andsecond amplifiers and the first and second phase shifters are coupled ina loop such that the frequency dependence of an impedance presented atthe output of the first amplifier emulates the impedance of a parallelRLC tank circuit. The circuit is expected to provide a Q of greater thanfifty at a center frequency ω_(o) of about five hundred megahertz.Significantly, the active frequency selection circuit may be formed as amonolithic CMOS or a BiCMOS integrated circuit. As a result, the activefrequency selection circuit may be combined with other kinds ofcircuits, such as signal processors and digital circuits.

[0010] Voltage dependent values for parasitic impedances and admittancesof the first and second amplifiers cause the center frequency ω_(o) tovary linearly with supply voltage. As a result, the center frequencyω_(o) can be swept over a range of tens or hundreds of megahertz byaltering the supply voltage.

[0011] In another aspect, the frequency selection circuit forms a tunedtransimpedance amplifier, with a second port coupled to the secondoutput of the second amplifier. The second port forms an output for thetransimpedance amplifier. The center frequency ω_(o) of the tunedtransimpedance amplifier also may be varied simply by varying the supplyvoltage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a simplified schematic diagram of an inductorless,voltage-tunable filter circuit, in accordance with an embodiment of thepresent invention.

[0013]FIG. 2 is a simplified schematic diagram of the inductorlessfilter circuit of FIG. 1, showing FETs to realize the current sourcesand active elements of the circuit of FIG. 1, in accordance with anembodiment of the present invention.

[0014]FIG. 3 is a graph of simulated input impedance and transimpedancefor the filter circuit of FIG. 2, in accordance with an embodiment ofthe present invention.

[0015]FIG. 4 is a graph showing simulated center frequency ω_(o) versuspower supply voltage for the circuit of FIG. 2, in accordance with anembodiment of the present invention.

[0016]FIG. 5 is a simplified schematic diagram of another embodiment ofan inductorless, voltage-tunable filter circuit, in accordance with anembodiment of the present invention.

[0017]FIG. 6 is a simplified schematic diagram of a self-biasing filtercircuit that is an embodiment of the filter circuit of FIG. 2, inaccordance with an embodiment of the present invention.

[0018]FIG. 7 is a simplified block diagram of a radio including tunedcircuits using the circuits of FIGS. 1, 2, 5 or 6, in accordance with anembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0019]FIG. 1 is a simplified schematic diagram of an inductorless,voltage-tunable filter circuit 10 constructed on a substrate 11, inaccordance with an embodiment of the present invention. The filtercircuit 10 includes an input 12 coupled to a first phase shift network13. In one embodiment, the first phase shift network 13 is formed from afirst capacitor 14 having a first capacitance C₁ coupled in shunt withthe input 12. The filter circuit 10 also includes a first current source16 coupled to a first current-carrying electrode 18 of a firsttransistor 20 forming a first amplifier 22. In one embodiment, the firsttransistor 20 is a FET configured as a source follower amplifier. Inanother embodiment, the first transistor 20 is a bipolar transistorconfigured as an emitter follower amplifier. In either case, the firstamplifier 22 provides a voltage gain at an amplifier output 24 of nearlyunity, together with high input impedance and relatively low outputimpedance. The output 24 of the first amplifier 22 is also coupled tothe input 12 to the filter circuit 10.

[0020] The first transistor 20 has a control electrode 26 coupled to asecond phase shift network 27. In one embodiment, the second phase shiftnetwork 27 is formed from a second capacitor 28 having a secondcapacitance C₂. The first transistor 20 has a second current-carryingelectrode 30 coupled to a voltage source V_(DD). The control electrode26 is coupled to an output 32 of a second amplifier 34. In oneembodiment, the second amplifier 34 is a common source FET amplifier. Inanother embodiment, the second amplifier 34 is a common emitteramplifier. The second amplifier 34 is formed from a second transistor 36having a first current-carrying electrode 38 that is grounded and asecond current-carrying electrode 40 coupled through a second currentsource 42 to the voltage source V_(DD). The second transistor 36 has acontrol electrode 44 forming an input 46 to the second amplifier 34. Thecontrol electrode 44 is also coupled to the output 24 of the firstamplifier 22.

[0021] In one embodiment, the first and second capacitors 14 and 28 arethin-film capacitors. In another embodiment, the first and secondcapacitors 14 and 28 are MOS capacitors, i.e., with one plate of thecapacitor 14 or 28 formed as a metallic or polysilicon contact on adielectric, such as a gate oxide, and the other plate of the capacitor14 or 18 formed as an inversion layer of minority charge carriers insemiconducting material on another side of the dielectric.

[0022]FIG. 2 is a simplified schematic diagram of a filter circuit 50 inaccordance with the embodiment of the inductorless filter circuit 10 ofFIG. 1. The filter circuit 50 uses FETs 52 and 54 to realize the firstand second current sources 16 and 42, and FETs 56 and 58 to realize thefirst and second transistors 20 and 36, respectively, of the circuit 10of FIG. 1. Many of the components used in the embodiment of the circuit50 of FIG. 2 are identical to components used in the embodiment of thecircuit 10 of FIG. 1. Therefore, in the interest of brevity, thesecomponents have been provided with the same reference numerals, and anexplanation of them will not be repeated.

[0023] For the filter circuit 50 of FIG. 2 where the first 20 and second36 transistors of FIG. 1 are FETs 56, 58 having transconductances gm₁and gm₂, respectively, circuit analysis shows that, to first order, thefilter circuit 50 has a center frequency ω_(o):

ω_(o)(gm ₁ ·gm ₂)/(C ₁ ·C ₂))^(0.5),  (1)

[0024] and a quality factor Q:

Q=((C ₁ gm ₂)/(C ₂ gm ₁))^(0.5),  (2)

[0025] when parasitic conductances and capacitances associated with thefirst 56 and second 58 FETs are ignored (i.e., G_(DS), C_(GS) etc.). Theratio of the center frequency ω_(o) to the Q gives the bandwidth B ofthe circuit as

B=ω _(o) /Q=gm ₁ /C ₂.  (3)

[0026] In one embodiment, the transconductance gm₁ of the FET 56 is5.2×10⁻⁵ Siemens, corresponding to a gate width of 1 micron, and thetransconductance gm₂ of the FET 58 is 5×10⁻³ Siemens, corresponding to agate width of 100 microns. When these parameters are coupled with valuesof C₁=1 picoFarad for the first capacitor 14 and C₂=30 femtoFarads forthe second capacitor 28, a center frequency ω_(o) of 468 megahertz isrealized together with a Q of 57, corresponding to a bandwidth B ofabout 10 megahertz. In many situations, a Q of greater than ten isdesirable and a Q of greater than 20 or 25 may be extremely desirable.In general, achieving Qs in this range requires that thetransconductance gm₁ of the FET 56 be less than one-tenth of thetransconductance gm₂ of the FET 58 and preferably substantially lessthan one-tenth of the transconductance gm₂.

[0027] In one embodiment, the FET 52 is an NMOS FET having the same gatewidth as an NMOS FET forming the FET 56, while the FET 54 is a PMOS FEThaving the same channel width as an NMOS FET forming the FET 58. Forsimplicity it is assumed the NMOS and PMOS have identical transistorcharacteristics. In some embodiments, the FETs 52 and 54 have theirgates 60 and 62 coupled to bias voltages at nodes 64 and 66,respectively. The bias voltages at nodes 64 and 66 may be provided byany conventional voltage source. Current sources 16 and 38 are preferredto supply current to the transistors 20 and 36, rather than, forexample, resistors, because a higher effective RF impedance is providedtogether with a relatively low supply voltage. In one embodiment, thecircuit 10 of FIG. 1 or the circuit 50 of FIG. 2 is formed using aconventional CMOS process. In another embodiment, the circuit 10 of FIG.1 or the circuit 50 of FIG. 2 is formed using a conventional BiCMOSprocess.

[0028]FIG. 3 is a graph of input impedance 70 (solid trace) andtransimpedance 72 (dashed trace), and FIG. 4 is a graph showing a trace80 representing center frequency ω_(o) versus power supply voltageV_(DD), for the circuit 50 of FIG. 2, in accordance with an embodimentof the present invention.

[0029] The source follower amplifier 22 of FIG. 2 is expected to have aninput impedance associated with the input 12 having a value of 1/gm₁ atthe resonance frequency ω_(o) corresponding to the peak in the solidtrace 70 of FIG. 3. The impedance at the input 12 generally behaves muchlike a parallel RLC tank circuit and may be employed in an analogousfashion in a receiver or transmitter circuit, as is discussed below withreference to FIG. 7. The filter circuit 50 of FIG. 2 may also be used asa transimpedance amplifier having the input 12 as an input port andusing the port 32 that is coupled to the drain 40 of the second FET 36as an output, corresponding to the dashed trace 72 of FIG. 3. The uppertrace 72 of FIG. 3 describes frequency dependence of an output voltageat the drain 40 of the second FET 36 divided by input current at theinput 12. A series of such gain stages 10 or 50 may be employed as avoltage-tunable RF amplifier chain in a TRF (tuned radio frequency)receiver or transmitter section. The trace 80 of FIG. 4 shows a lineardependence of center frequency ω_(o) on supply voltage VDD, with a sweeprate of about 50 megahertz per volt, and also shows a broad range offrequencies over which the circuit 50 may be tuned. It will beappreciated that other frequency ranges may be realized by alteringvalues for components in the circuit 50.

[0030]FIG. 5 is a simplified schematic diagram of another embodiment ofan inductorless, voltage-tunable filter circuit 90, in accordance withthe present invention. The filter circuit 90 includes bipolartransistors 92 and 94 as the first 20 and second 36 transistors of FIG.1, and may employ bipolar transistors or FETs to provide the first andsecond current sources 16 and 42. When the first transistor 20 is abipolar transistor, a base bias current must be supplied to the controlelectrode 26. In one embodiment, a phase shift network 96 includes abias source, such as a high value resistor or other conventional biassource. Similarly, when the second transistor 36 is a bipolar transistor94, a base bias current must be supplied. In one embodiment, the basebias current is supplied through a conventional bias network 98, such asa resistor. The circuit 90 may be fabricated using a conventional BiCMOSprocess in one embodiment.

[0031]FIG. 6 is a simplified schematic diagram of an embodiment of aself-biasing filter circuit 100 according to the embodiment of thefilter circuit 50 of FIG. 2. The self-biasing filter circuit 100 employsa resistive divider network 102 to provide a pair of gate bias voltagesV_(GG1) and V_(GG2) that maintain a fixed ratio as the power supplyvoltage V_(DD) is varied to tune the center frequency ω_(o). Theresistive divider network 102 includes a first resistor 104 having afirst terminal coupled to a variable supply voltage V_(DD) and a secondterminal coupled to the gate 62 of the FET 54 forming the second currentsource 42. A second resistor 106 has a first terminal coupled to thesecond terminal of the first resistor 104 and a second terminal coupledto the gate 60 of the FET 52 forming the first current source 16. Athird resistor 108 has a first electrode coupled to the second electrodeof the second resistor 106 and a second electrode coupled to ground. Asa result, the ratio of the gate bias voltage V_(GG1) on the FET 52 tothe gate bias voltage V_(GG2) on the FET 54 is constant with changingV_(DD). In turn, the currents through the other transistors 20 and 36vary together as V_(DD) changes.

[0032] As a result, a simple circuit 100 is realized that provides acenter frequency ω_(o) that may be varied over a relatively broadfrequency range in response to a simple voltage change. The circuit 100lends itself to monolithic fabrication, allowing it to be formed on anintegrated circuit that is also able to support logic and otherfunctions.

[0033]FIG. 7 is a simplified block diagram of a radio 120 includingtuned RF amplifiers and/or filters using the circuits 10, 50, 90 or 100of FIGS. 1, 2, 5 or 6, respectively, in accordance with embodiments ofthe present invention. The radio 120 includes an antenna 122 fortransmitting and receiving signals. The antenna 122 is coupled to anoptional T/R switch or duplexer 124 that may be needed to separatesignals originating in an optional transmitter section 126 from signalsintended for a receiver section 128. The receiver section 128 mayinclude an optional filter 130 that accepts RF input signals from theantenna 122 and typically includes one or more radio frequencyamplifiers 132, 134 (marked “RF AMP” in FIG. 7) coupled in series. Amixer 136 mixes signals from the amplifiers RF AMP 132, 134 with signalsfrom a local oscillator LO 138 to provide baseband or IF signals thatare then processed and demodulated by a signal processor DEMOD 140 toprovide an output signal at an output 142. The signal at the output 142may be an IF signal, a visual or audible annunciation, for example whenthe receiver section 128 forms a portion of a paging device or portabletelephone, or may be digital data or voice signals in otherapplications.

[0034] In those applications where the transmitter section 126 is also aportion of the radio 120, input data from an input 150 is processed in asignal processor MOD 152 that typically includes a modulator and thatmay include other functions. An output signal from the signal processorMOD 152 is mixed with a signal from the local oscillator LO 138 in amixer 154 to provide radio frequency signals. The radio frequencysignals are typically amplified in a radio frequency amplifier RF AMP156 and are routed to the antenna 122 for transmission.

[0035] In the radio 120, the optional filter 130 may be a conventionalpassive filter or may be any of the circuits 10, 50, 90 or 100 of FIGS.1, 2, 4 or 6, respectively. In some applications, a passive filteroffers intermodulation advantages, while in others, noise figure is adominating concern, requiring a low noise gain block coupled to theantenna 122. The radio frequency amplifiers RF AMP 132, 134, 156 may beconventional RF amplifiers that are tuned by having the input 12 (FIGS.1, 2, 4, 6) coupled to the signal path or may be transimpedanceamplifiers having inputs 12 and outputs 32. Either topology may beemployed to provide a tuned radio frequency amplifier chain. In eithertopology, independent control of the supply voltages allows independentadjustment of the center frequencies of the radio frequency amplifiersRF AMP 132, 134, 156.

[0036] In some embodiments, a conventional digital-to-analog converter(not illustrated) may be employed to supply the variable supply voltageV_(DD) under control of a conventional microprocessor (not illustrated).This allows the center frequency ω_(o) to be set in response to externalcommands or in response to variables sensed within the system containingthe circuits 10, 50, 90 or 100 or the radio 120.

[0037] An advantage to radios 120 using the circuits 10, 50, 90 or 100is that many, if not all, of the functions of the radio 120 may berealized through one or more integrated circuits. As a result, the radio120 may be manufactured using less labor together with improvedfootprint, reduced weight, greater reliability and reduced powerconsumption, and in a very compact package. The radio 120 may also becombined with other functional blocks in a single integrated circuit.

[0038] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. An active frequency selection circuit comprising: a first port havinga frequency-dependent input impedance; a first amplifier configured toprovide nearly unity gain, a high input impedance and a low outputimpedance, the first amplifier having a first input and a first output,the first output coupled to the first port; a first capacitor coupledbetween the first port and a reference voltage; a second amplifierconfigured to provide greater than unity voltage gain, the secondamplifier having a second input coupled to the first output and a secondoutput coupled to the first input; and a second capacitor coupledbetween the second output and a reference voltage.
 2. The circuit ofclaim 1 wherein the first amplifier is a source follower amplifier andthe second amplifier is a common source amplifier.
 3. The circuit ofclaim 1 wherein the first amplifier includes a first transistor having afirst power electrode coupled to a power supply, a second powerelectrode coupled to a first current source and to the first output anda control electrode coupled to the first input, and the second amplifierincludes a second transistor having a first power electrode coupled toground, a second power electrode coupled to a second current source andto the second output and a control electrode coupled to the secondinput, and the first and second current sources are formed fromtransistors.
 4. The circuit of claim 1 wherein the first and secondamplifiers are formed on a single CMOS integrated circuit.
 5. Thecircuit of claim 1 wherein the first and second amplifiers are formed ona single BiCMOS integrated circuit.
 6. The circuit of claim 1 whereinthe first and second amplifiers are formed on a single integratedcircuit.
 7. The circuit of claim 1 wherein the first amplifier includesa first transistor having a first transconductance, the second amplifierincludes a second transistor having a second transconductance and thefirst transconductance is about one one-hundredth of the secondtransconductance.
 8. The circuit of claim 1 , further comprising asecond port coupled to the second output, the first port forming afilter input and the second port forming a filter output.
 9. The circuitof claim 1 wherein a center frequency of the circuit varies with supplyvoltage.
 10. The circuit of claim 1 wherein the first and secondcapacitors are thin-film capacitors.
 11. The circuit of claim 1 whereinthe first and second capacitors are MOS capacitors.
 12. An inductorlessmonolithic voltage tunable filter circuit comprising: first amplifiermeans having a first input and a first output, a first input impedanceassociated with the first input being much less than a first outputimpedance associated with the first output, the first amplifier meanshaving a voltage gain of slightly less than one; second amplifier meanshaving a second input and a second output, a second input impedanceassociated with the second input being much larger than a second outputimpedance associated with the second output, the second amplifier meanshaving a voltage gain of greater than one, the second input beingcoupled to the first output to form a filter input; first phase shiftingmeans coupled to the output of the second amplifier means and the inputof the first amplifier means; and second phase shifting means coupled tothe filter input, the first phase shifting means, the second phaseshifting means, the first amplifier means and the second amplifier meansfor collectively providing a frequency dependent impedance at the filterinput.
 13. The filter circuit of claim 12 wherein the first amplifiermeans comprises: a source follower amplifier including a first FEThaving a gate coupled to the first input, a drain coupled to a powersupply and a source coupled to the first output; and a current sourcehaving a first terminal coupled to ground and a second terminal coupledto the first input.
 14. The filter circuit of claim 12 wherein the firstamplifier means comprises: a source follower amplifier including a firstFET having a gate coupled to the first input, a drain coupled to a powersupply and a source coupled to the first output; and a second FET havinga source coupled to ground, a drain coupled to the first input and agate coupled to a voltage source biasing the second FET to provide aconstant current source.
 15. The filter circuit of claim 12 wherein thefirst amplifier means comprises: an emitter follower amplifier includinga first bipolar transistor having a base coupled to the first input, acollector coupled to a power supply and an emitter coupled to the firstoutput; and a current source having a first terminal coupled to groundand a second terminal coupled to the first input.
 16. The filter circuitof claim 12 wherein the second amplifier means comprises: a commonsource amplifier including a first FET having a source coupled toground, a drain coupled to the second output and a gate coupled to thesecond input; and a current source having a first terminal coupled to areference voltage and a second terminal coupled to the drain of thefirst FET.
 17. The filter circuit of claim 12 wherein the phase shiftingmeans comprises a capacitor having a first lead coupled to RF ground anda second lead coupled to the first amplifier means output and the secondamplifier means input.
 18. The filter circuit of claim 12 wherein thefirst amplifier means, the second amplifier means, the first phaseshifting means and the second phase shifting means comprise a CMOSintegrated circuit.
 19. The filter circuit of claim 12 wherein the firstamplifier means, the second amplifier means, the first phase shiftingmeans and the second phase shifting means comprise a BiCMOS integratedcircuit.
 20. The filter circuit of claim 12 , further comprising afilter output coupled to the second output.
 21. The filter circuit ofclaim 12 wherein: the first amplifier means comprises a source followeramplifier formed from a first FET having a first gate width; and thesecond amplifier means comprises a common source amplifier formed from asecond FET having a second gate width approximately one hundred timeslarger than the first gate width.
 22. The filter circuit of claim 12wherein the first amplifier means, the second amplifier means, the firstphase shifting means and the second phase shifting means collectivelyform a transimpedance filter amplifier having a center frequency that isapproximately linearly proportional to a supply voltage coupled to thefilter circuit, the transimpedance amplifier having an input coupled tothe first output and having an output coupled to the second output. 23.A monolithic frequency selective component comprising: a substrate; afirst port having a voltage-variable frequency-dependent inputimpedance; a first FET amplifier formed on the substrate, configured asa source follower and having an output coupled to the first port, thefirst FET amplifier including: a first FET having a first gate width andincluding a source coupled to the output of the first FET amplifier, adrain coupled to a power supply and a gate coupled an input to the firstFET amplifier; and a second FET having the first gate width andincluding a source coupled to ground, a gate and a drain coupled to thesource of the first FET; a first phase shift network formed on thesubstrate and coupled to the first port; a second phase shift networkformed on the substrate and coupled to the input to the first FETamplifier; and a second FET amplifier formed on the substrate and havingan output coupled to the second phase shift network and an input coupledto the output of the first FET amplifier, the second FET amplifierincluding: a third FET having a second gate width and including a sourcecoupled to ground, a drain and a gate coupled to the input to the secondFET amplifier; and a fourth FET having the second gate width andincluding a drain coupled to the power supply, a gate and a sourcecoupled to the drain of the second FET; and a bias network coupled tothe gates of the second and fourth FETs.
 24. The component of claim 23wherein the first gate width is about one one-hundredth of the secondgate width.
 25. The component of claim 23 wherein: the first phase shiftnetwork includes a thin-film capacitor having a first electrode coupledto the first port and a second electrode coupled to RF ground; and thesecond phase shift network includes a thin-film capacitor having a firstelectrode coupled to the input of the first FET amplifier and a secondelectrode coupled to RF ground.
 26. The component of claim 23 whereinthe bias network comprises: a first resistor having a first electrodecoupled to ground and a second electrode coupled to the gate of thesecond FET; a second resistor having a first electrode coupled to thesecond electrode of the first resistor and a second electrode coupled tothe gate of the fourth FET; and a third resistor having a firstelectrode coupled to the gate of the fourth FET and a second electrodecoupled to a power supply.
 27. The component of claim 23 wherein thefirst, second and third FETs are n-channel FETs and the fourth FET is ap-channel FET.
 28. The component of claim 23 wherein the first FET has afirst transconductance and the third FET has a second transconductancethat is more than ten times the first transconductance.
 29. Thecomponent of claim 23 wherein the first FET has a first transconductanceand the third FET has a second transconductance approximately onehundred times the first transconductance.
 30. The component of claim 23, further comprising a second port coupled to the output of the secondFET amplifier, where the first port forms a filter input and the secondport forms a filter output.
 31. The component of claim 23 wherein thefirst FET has a first transconductance gm₁, the third FET has a secondtransconductance gm₂, the first phase shift network includes a firstcapacitor having a capacitance C₁, the second phase shift networkincludes a second capacitor having a capacitance C₂ and the componenthas a quality factor Q=((C₁gm₂)/(C₂ gm₁))⁰⁵ that is greater than
 10. 32.The component of claim 23 wherein the first and second FET amplifiersare formed by a CMOS process.
 33. The component of claim 23 wherein thefirst and second FET amplifiers are formed by a BiCMOS process.
 34. Amonolithic radio frequency circuit comprising: an RF input; a RFamplifier including an input coupled to the RF input, an output and avoltage-tunable frequency selection component; a mixer having a firstinput coupled to the output of the RF amplifier; a local oscillatorhaving an output coupled to a second input to the mixer; and a basebandsignal processor having an input coupled to an output of the mixer andhaving an output coupled to a user interface.
 35. The circuit of claim34 wherein the RF amplifier comprises: a first port presenting afrequency-dependent impedance coupled to the input of the RF amplifier;a first amplifier configured to provide nearly unity gain, a high inputimpedance and a low output impedance, the first amplifier having a firstinput and a first output, the first output coupled to the first port; afirst capacitor coupled between the first port and a reference voltage;a second amplifier configured to provide greater than unity voltagegain, the second amplifier having a second input coupled to the firstoutput and a second output coupled to the first input; and a secondcapacitor coupled between the second output and a reference voltage. 36.The circuit of claim 34 wherein the RF amplifier comprises: firstamplifier means having a first input and a first output, a first inputimpedance associated with the first input being much less than a firstoutput impedance associated with the first output, the first amplifiermeans having a voltage gain of slightly less than one, the first outputcoupled to the input of the RF amplifier; second amplifier means havinga second input and a second output, a second input impedance associatedwith the second input being much larger than a second output impedanceassociated with the second output, the second amplifier means having avoltage gain of greater than one, the second input being coupled to thefirst output to form a filter input; first phase shifting means coupledto the output of the second amplifier means and the input of the firstamplifier means; and second phase shifting means coupled to the filterinput, the first phase shifting means, the second phase shifting means,the first amplifier means and the second amplifier means forcollectively providing a frequency dependent impedance at the filterinput.
 37. The circuit of claim 34 wherein the RF amplifier includes amonolithic frequency selective component comprising: a substrate; afirst port displaying a voltage-variable frequency-dependent impedancecharacteristic coupled to the input to the RF amplifier; a first FETamplifier formed on the substrate, configured as a source follower andhaving an output coupled to the first port, the first FET amplifierincluding: a first FET having a first gate width and including a sourcecoupled to the output of the first FET amplifier, a drain coupled to apower supply and a gate coupled an input to the first FET amplifier; anda second FET having the first gate width and including a source coupledto ground, a gate and a drain coupled to the source of the first FET; afirst phase shift network formed on the substrate and coupled to thefirst port; a second phase shift network formed on the substrate andcoupled to an input to the first FET amplifier; and a second FETamplifier formed on the substrate and having an output coupled to thesecond phase shift network and an input coupled to the output of thefirst FET amplifier, the second FET amplifier including: a third FEThaving a second gate width and including a source coupled to ground, adrain and a gate coupled to the input to the second FET amplifier; and afourth FET having the second gate width and including a drain coupled toa power supply, a gate and a source coupled to the drain of the secondFET; and a bias network coupled to the gates of the second and fourthFETs.
 38. A method of operating a monolithic frequency selectioncomponent comprising: providing a first FET amplifier configured as asource follower and having a first transconductance gm₁; providing asecond FET amplifier configured as a common source amplifier and havinga second transconductance gm₂; providing a first capacitor having afirst lead coupled to an output of the second FET amplifier and to aninput of the first FET amplifier, the first capacitor having acapacitance C₁; providing a second capacitor having a second capacitanceC₂ and including a first lead coupled to an output of the first FETamplifier; and setting a supply voltage for the first and second FETamplifiers to a voltage that causes a frequency response at the outputof the first FET amplifier to have a first center frequency ω_(o1) ofapproximately ((gm₁gm₂)/(C₁C₂))⁰ ⁵.
 39. The method of claim 38 , furthercomprising setting a Q of the frequency response to be approximatelyQ=((C₁gm₂)/(C₂·gm₁))⁰ ⁵.
 40. The method of claim 39 wherein the act ofsetting a Q includes setting the Q to be greater than
 10. 41. The methodof claim 38 , further comprising resetting the supply voltage to causethe frequency response at the output of the first FET amplifier to havea second center frequency ω_(o2) different than the first centerfrequency ω_(o1).